Improved Handling of the Decoding Operation in the Presto Compiler

This thesis presents a research project on decoder related optimizations in HDL designs. The goal of the reasearch is to improve design synthesis quality-of-result, mainly in terms of area; this involves sharing decoders driven by related inputs, and map decoders using fewer number of boolean gates. Algorithms presented in this thesis were implemented in the Presto HDL compiler. A series of tests were conducted using real-world HDL designs in order to determine how effective these optimizations are. Thesis Supervisor: Karen Pieper Title: VI-A Company Thesis Supervisor Thesis Supervisor: Arvind, Johnson Professor Title: M.I.T. Thesis Supervisor